History of the SPARC CPU Architecture

History of the SPARC CPU Architecture

[RetroBytes] nicely presents the curious history of the SPARC processor architecture. SPARC, short for Scalable Processor Architecture, defined some of the most commercially successful RISC processors during the 1980s and 1990s. SPARC was initially developed by Sun Microsystems, which most of us associate the SPARC but while most computer architectures are controlled by a single company, SPARC was championed by dozens of players.  The history of SPARC is not simply the history of Sun.

A Reduced Instruction Set Computer (RISC) design is based on an Instruction Set Architecture (ISA) that runs a limited number of simpler instructions than a Complex Instruction Set Computer (CISC) based on an ISA that comprises more, and more complex, instructions. With RISC leveraging simpler instructions, it generally requires a longer sequence of those simple instructions to complete the same task as fewer complex instructions in a CISC computer. The trade-off being the simple (more efficient) RISC instructions are usually run faster (at a higher clock rate) and in a highly pipelined fashion. Our overview of the modern ISA battles presents how the days of CISC are essentially over.

IBM may have been the first player exploring RISC processor concepts, however work by two different university groups was more visible and thus arguably more influential. The Stanford group commercialized into MIPS  and Berkeley RISC commercialized into SPARC.

SPARC Versions 7 and 8, the first two versions of SPARC, were 32 bit architectures. Evolution to SPARC Version 9 jumped up to 64 bits but preserved backward compatibility. While having 64 bit registers, legacy 32 bit instructions operated identically as they had in previous versions.  Only a handful of new 64 bit instructions were required and those automatically made use of the upper 32 bits. Other advancements in SPARC Version 9 exploited knowledge from existing code to identify performance improvements. These included cache prefetch, data misalignment handling, and conditional moves to reduce branching. Other major improvements in SPARC Version 9 boosted OS performance.  These included instruction privileges, register privileges, and multiple trap levels.

The SPARC Version 9 improvements were defined by SPARC International, members of which include Sun Microsystems, Fujitsu, Texas Instruments, Cray, Ross, and others.  Sun was a significant part of SPARC International, but they did not go it alone.

Since SPARC Version 9, progress has mostly focused on multiprocessing with Fujitsu still manufacturing SPARC-based mainframes. SPARC has also become open and royalty free and found a footing in embedded computing.  Some have even synthesized SPARC processors onto inexpensive FPGAs.